Source
- URL: https://x.com/MissQuickstep/status/1682066496304955393
- Author: Layla Mah @missquickstep@mastodon.gamedev.place (@MissQuickstep)
- Posted: 2023-07-20 16:34:38
Thread
1/ @MissQuickstep
Cache hit rate - PS runs in hardware order (probably Morton Z-Order), CS runs in linear order.
Branches: 2023-07-21-sopyer-could-be-but-with-linear-order-and-linear-layour, 2023-07-21-kenpex-not-only-on-lots-of-hw-the-rop-caches-can-be
2/ @vassvik
@MissQuickstep
Shouldn’t make a big difference in practice. A compute shader has spatial grouping where most waves/warps will sample adjacent memory and hit relatively high bandwidth and cache utilization even in the naive implementations.
No way 512x512 is BW/cache bound, though
3/ @NOTimothyLottes
@vassvik @MissQuickstep
You can look at what I did for CAS/FSR1/etc: Simplified {64,1,1} to {8x8} lane remapping (so 4x1 lanes map to a 2x2), semi-persistent waves to avoid wait on store complete for wave relaunch and get better L0$2work mapping, etc. Have to make sure DCC matches (PS vs CS paths). Etc.