Source
- URL: https://x.com/NOTimothyLottes/status/2085365714412556730
- Author: NOTimothyLottes (@NOTimothyLottes)
- Posted: 2026-08-06 14:01:45
Thread
1/ @NOTimothyLottes
Seems like one of the pain points with Xlinix DSPs that if you want either a 32-bit ADD or a MAD you need to CLB the A B inputs differently due to how the ADD path takes A:B and the MUL takes A,B.
2/ @NOTimothyLottes
In my case the top 4-bit MSBs of operands already use a 8:1 mux so im out of single pipeline stage CLB. Puts the design back into the slow burn on break rethink mode …
Branches: 2026-08-06-NOTimothyLottes-at-least-with-ultrascale-if-you-can-afford-to-run
3/ @NOTimothyLottes
The aim was to place a sub-word decode pipeline stage (CLB) between a direct mapped shift register (SLICEM) to DSP inputs for operand fetch. With shift register getting a program controlled MUX as input/clk …
4/ @NOTimothyLottes
… that mux taking things like bits of P, operands conditional to the sign bit of P (for 1 clk compare and swap), BRAM read, etc. But each of the 3 gets separate CE and mux choice. So functions like 32 entry 3 bank registers file.
5/ @NOTimothyLottes
So in register sorting actually works out at 1 clk per compareswap. Because it’s a 3 bank store, and one can bank swap too on the swap.
6/ @NOTimothyLottes
In some ways this is an evolution of forth where the data stack transforms into multi bank and one replaces the stack with an indexable looping queue (without a pop).
7/ @NOTimothyLottes
Note sub-word extract is right justified (fills MSBs) and left side gets zero fill. Far better than the left justified zero/sign extraction, but requires a IMAD fixed shift (fixed point op).