Source
- URL: https://x.com/SebAaltonen/status/1898272635277967509
- Author: Sebastian Aaltonen (@SebAaltonen)
- Posted: 2025-03-08 07:20:39
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1/ @SebAaltonen
Stupid hardware question: Why does AMD use several counters instead of one u64 bitmask for memory ops?
Each load/store would have a bit index and wait would have a bitmask (marked bits need to be set = finished).
Branches: 2025-03-08-NOTimothyLottes-actually-this-is-a-super-important-question-imo
2/ @SebAaltonen
I am glad that RDNA4 has separate counters for sampling (long latency) and lower latency raw loads now. That’s a good improvement.
3/ @SebAaltonen
Some thoughts: Compiler managed bitfield slot indices would be iffy with loops and branches. One bit per register (big bitfield) would always work, but that would be much more than 64 bits. And wait instructions would be iffy (how to describe a massive bitfield).