Source
- URL: https://x.com/tribbloid/status/1811804116877799564
- Author: Peng Cheng, asking λP2-λC (@tribbloid)
- Posted: 2024-07-12 16:45:37
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1/ @tribbloid
@VictorTaelin
horrible idea: if you want to rewrite circuit for performance, why not doing it directly on the lowest gate-level?
mainstream adders (Kogge-Stone) and multipliers (Wallace) are quite suboptimal, but the only superhuman rewrite I knew is based on e-graph
https://arxiv.org/abs/2312.06004
2/ @VictorTaelin
@tribbloid
What do you mean is a terrible idea exactly? A processor with millions of interaction cores?
3/ @tribbloid
@VictorTaelin
sorry I mean “doing it on gate-level” may be a horrible idea
4/ @VictorTaelin
@tribbloid
but I don’t get what you mean? what the alternative would be?
5/ @tribbloid
@VictorTaelin
IMHO most tools focus on optimising RTL then delegate to HLS
(from arXiv) High-level and logic synthesis tools … but rely on fixed architectures …
if optimising gate-level directly (e.g. rewriting a ripple-carry adder into Kogge-Stone), then HLS will be slow in comparison
6/ @tribbloid
@VictorTaelin
correction: delegate to LS (which will be slow in comparison)
LS and HLS are not the same thing (excuse my English)