Source
- URL: https://x.com/b1tcminerpljy/status/1457781649869991936
- Author: Nelsoncoindigger (@b1tcminerpljy)
- Posted: 2021-11-08 18:46:44
Branch
1/ @b1tcminerpljy
@ID_AA_Carmack
Interesting recent development has been ‘writing’ hardware in Python, e.g. ‘Migen’, for FPGAs/ASICs instead of traditional VHDL/Verilog which are old & v. clunky.